Instructions in microprocessors are often re-dispatched for execution one or more times due to pipeline errors or data hazards. For example, an instruction may need to be re-dispatched when an instruction refers to a value not present in the cache (e.g., a cache miss). Because it is not known whether other unpredicted stalls will arise due to other misses during resolution of that cache miss, the microprocessor may perform a runahead operation configured to detect other misses while the initial miss is being resolved. However, the calculations performed during runahead are often invalidated and repeated. Repeating these calculations after re-entry into normal operation mode may diminish microprocessor performance.